cystech electronics corp. spec. no. : c700a3 issued date : 2008.02.22 revised date :2012.10.16 page no. : 1/6 BCR1002A3 cystek product specification pnpn epitaxial planar scr BCR1002A3 descriptions the BCR1002A3 is designed for high volume consumer a pplications such as temperature, light, and speed control; process and remote control, and warning systems where reliability of operation is important. features ? practical level triggering and holding characteristics ? on state current rating of 0.35a rms ? sensitive gate allows triggering by microcontrollers and other logic circuits ? pb-free package symbol outline BCR1002A3 to-92 ordering information device package shipping BCR1002A3-0-tb-g to-92 (pb-free lead plating an d halogen-free package) 2000 pcs / tape & box BCR1002A3-0-bk-g to-92 (pb-free lead plating an d halogen-free package) 1000 pcs / bag; 10 bags/box, 10 boxes/carton g gate a anode k cathode k g a
cystech electronics corp. spec. no. : c700a3 issued date : 2008.02.22 revised date :2012.10.16 page no. : 2/6 BCR1002A3 cystek product specification absolute maximum ratings (t j =25 c) parameter symbol limits unit peak repetitive off-state voltage @t j =-40 to 125 , r gk =1k v drm 140 v on-state current @t c =80 i t(rms) 350 ma average on-state current @ t c =80 i t(av) 220 ma peak non-repetitive surge current, half cycle, sine wave, 60hz i tsm 4 a circuit fusing consideration (t=8.3ms) i 2t 0.2 a 2s reverse peak gate voltage @t a =25 , pulse width 1 s v grm 8 v forward peak gate current @t a =25 , pulse width 1 s i gm 500 ma forward average gate power @ t a =25 , t=8.3ms p g(av) 100 mw thermal resistance, junction to ambient r ja 200 c/w thermal resistance, junction to case r jc 75 c/w junction temperature tj -40~+125 c storage temperature tstg -40~+150 c lead solder temperature(<1/16? from case, 10secs max) t l 260 c note : stress exceeding maximum ratings may damage the de vice. maximum ratings are st ress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. v drm can be applied on a continuous basis. ratings apply for zero or negative gate voltage; however , positive gate voltage shall not be applied concurrent with negative potential on the anode. blocking voltage shall not be tested with a constant current source such that the voltage ratings of the device are exceeded. characteristics (ta=25 c) symbol min. typ. max. unit test conditions i drm - - 100 a v d =140v, r gk =1k , t c =125 i drm - - 10 a v d =140v, r gk =1k , t c =25 *v tm - - 1.5 v i tm =200ma i gt - - 100 a v d =7v, r l =100 i h - - 5 ma v d =7v, r gk =1k i l - - 6 ma v d =7v, i g =200 a v gt - - 0.8 v v d =7v, r l =100 dv/dt 25 - - v/ s v d =35v, r gk =1k di/dt 30 - - a/ s i g =10ma, di g /dt=100ma/ s, p w =10 s *pulse test: pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c700a3 issued date : 2008.02.22 revised date :2012.10.16 page no. : 3/6 BCR1002A3 cystek product specification typical characteristics gate trigger current vs junction temperature 0 10 20 30 40 50 60 70 -50 -25 0 25 50 75 100 125 junctiontemperature---t j () gate trigger current---i gt ( a) gate trigger voltage vs junction temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -50-250 255075100125 junction temperature---t j (c) gate trigger voltage---v gt (v) holding current vs junction temperature 0.1 1 10 -50 -25 0 25 50 75 100 125 junction temperature---t j (c) holding current---i h (ma) latching current vs junction temperature 10 100 1000 -50 -25 0 25 50 75 100 125 junction temperature---t j (c) latching current---i l ( a) on-state characteristics 10 100 1000 00.40.81.21.62 instantaneous on-state voltage---v t (v) instantaneous on-state current---i t (ma) t j =-40c t j =25c t j =125c
cystech electronics corp. spec. no. : c700a3 issued date : 2008.02.22 revised date :2012.10.16 page no. : 4/6 BCR1002A3 cystek product specification to-92 taping outline millimeters dim item min. max. a component body height 4.33 4.83 d tape feed diameter 3.80 4.20 d1 lead diameter h2a h2a h2 h2 d2 a h w w1 h3 h4 h1 l1 l p2 p p1 f1 f2 d1 d t2 t t1 0.36 0.53 d2 component body diameter 4.33 4.83 f1,f2 component lead pitch 2.40 2.90 f1,f2 f1-f2 - 0.3 h height of seating plane 15.50 16.50 h1 feed hole location 8.50 9.50 h2 front to rear deflection - 1 h2a deflection left or right - 1 h3 component height - 27 h4 feed hole to bottom of component - 21 l lead length after component removal - 11 l1 lead wire enclosure 2.50 - p feed hole pitch 12.50 12.90 p1 center of seating plane location 5.95 6.75 p2 4 feed hole pitch 50.30 51.30 t over all tape thickness - 0.55 t1 total taped package thickness - 1.42 t2 carrier tape thickness 0.36 0.68 w tape width 17.50 19.00 w1 adhesive tape width 5.00 7.00 - 20 pcs pitch 253 255
cystech electronics corp. spec. no. : c700a3 issued date : 2008.02.22 revised date :2012.10.16 page no. : 5/6 BCR1002A3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 217 c 60-150 seconds 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c700a3 issued date : 2008.02.22 revised date :2012.10.16 page no. : 6/6 BCR1002A3 cystek product specification to-92 dimension *: typical inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1704 0.1902 4.33 4.83 g 0.0142 0.0220 0.36 0.56 b 0.1704 0.1902 4.33 4.83 h - * 0.1000 - * 2.54 c 0.5000 - 12.70 - i - * 0.0500 - * 1.27 d 0.0142 0.0220 0.36 0.56 1 - * 5 - * 5 e - * 0.0500 - * 1.27 2 - * 2 - * 2 f 0.1323 0.1480 3.36 3.76 3 - * 2 - * 2 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance . r1002 3 1 a d b c i 1 e f 2 3 g h 2 marking: s t yle: pin 1.c a thode 2.g a te 3.anode 3-l ead t o -9 2 plastic pa ckag e cys t ek pa ck a g e code: a 3 product name date code: y ear+month y ear: 4 2004, 5 20 05 month: 1 1, 2 2, ??? , 9 9, a 10, b 11 , c 12
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